Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms
LaoBiz.com profiles the Laos Patent “Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms” from open registry fields, filed by QUALCOMM INCORPORATED on 2015-12-17; current status: Registered. Identifiers include application No. P/515; DIP id LAP515; protection kind Patent - PCT National Phase. Key dates: publication 2023-07-14; grant 2023-07-10; expiry reference 2035-12-17. Classification: G06F 13/16、H01L 25/065. Inventor(s)/designer(s): CHATHA, Karamvir, Singh, DU, Yang, LIM, Sung, Kyu, SAMADI, Kambiz. Abstract hint: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC…. Status labels may change after office actions; refresh or consult primary DIP data before commercial decisions.
P/515
Mark
Key facts
- Type
- Patent
- App. no.
P/515- Status
- Registered
- Applicant
- QUALCOMM INCORPORATED
- Agent
- CONCETTI-LAO CO., LTD
- Filing date
- 2015-12-17
- Reg. no.
P/515- Publication
- 2023-07-14
- Registration / grant
- 2023-07-10
- Expiry
- 2035-12-17
- Protection kind
- Patent - PCT National Phase
- Gazette
- 215 · 2023-07-14
- Priority
- US · 14/602,505 · 2015-01-22；US · PCT/2015/066334 · 2015-12-17
- Applicant address
- QUALCOMM INCORPORATED · Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 · US
- Agent address
- CONCETTI-LAO CO., LTD · Lao-Thai Friendship Road, Sokpaluang Village,Sisattanak District, Vientiane Lao PDR, Tel: 312 383 · LA
- Nice / IPC classes
- G06F 13/16 · H01L 25/065
- Goods / services
- —
Process
Steps follow the current public status-
Filed
-
Formal examination
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Substantive examination
-
Published
-
Granted
Related records
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Abstract
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
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