Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms
本页收录老挝专利「Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms」的公开登记要点，由 QUALCOMM INCORPORATED 于 2015-12-17 提交申请，当前状态为已注册。关键编号与类型标注为 申请号 P/515 / DIP 编号 LAP515 / 主管局代码 LA / 保护类型 Patent - PCT National Phase。时间线要点：公开/公告日 2023-07-14；授权日 2023-07-10；届满/失效参考日 2035-12-17。技术或外观分类记载为 G06F 13/16、H01L 25/065。发明人 / 设计人包括 CHATHA, Karamvir, Singh、DU, Yang、LIM, Sung, Kyu、SAMADI, Kambiz。代理机构 / 代理人记载为 CONCETTI-LAO CO., LTD。公开摘要提示：Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC…。
P/515
图样
基础信息
- 类型
- 专利
- 申请号
P/515- 状态
- 已注册
- 申请人
- QUALCOMM INCORPORATED
- 代理机构
- CONCETTI-LAO CO., LTD
- 申请日期
- 2015-12-17
- 注册号
P/515- 公开 / 公告日
- 2023-07-14
- 注册 / 授权日
- 2023-07-10
- 到期日
- 2035-12-17
- 保护类型
- Patent - PCT National Phase
- 公报号
- 215 · 2023-07-14
- 优先权
- US · 14/602,505 · 2015-01-22；US · PCT/2015/066334 · 2015-12-17
- 申请人地址
- QUALCOMM INCORPORATED · Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 · US
- 代理地址
- CONCETTI-LAO CO., LTD · Lao-Thai Friendship Road, Sokpaluang Village,Sisattanak District, Vientiane Lao PDR, Tel: 312 383 · LA
- 国际分类
- G06F 13/16 · H01L 25/065
- 商品 / 服务
- —
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摘要
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
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