Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms
专利「Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms」由 QUALCOMM INCORPORATED 持有，当前状态为已注册，申请号 P/515。LaoBiz 老商通提供老挝知识产权信息检索与企业关联查询。
Patent “Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms” is held by QUALCOMM INCORPORATED; status: 已注册. Search Laos IP records on LaoBiz.
P/515
图样
基础信息
- 类型
- 专利
- 申请号
P/515- 状态
- 已注册
- 申请人
- QUALCOMM INCORPORATED
- 代理机构
- CONCETTI-LAO CO., LTD
- 申请日期
- 2015-12-17
- 注册号
P/515- 公开/公告日
- 2023-07-14
- 注册/授权日
- 2023-07-10
- 届满日
- 2035-12-17
- 国际分类
- G06F 13/16 · H01L 25/065
- 商品 / 服务
- —
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摘要
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.