Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms
ກ່ຽວກັບ ສິດທິບັດ «Memory controller placement in a three-dimensional (3D) integrated circuit (IC)(3DIC) employing distributed through-silicon-silicon-via (TSV) farms» ໃນລາວ, ຍື່ນໂດຍ QUALCOMM INCORPORATED ໃນວັນທີ 2015-12-17; ສະຖານະ ຈົດທະບຽນແລ້ວ. ຕົວລະບຸ: ເລກທີຄຳຮ້ອງ P/515; ລະຫັດ DIP LAP515; ປະເພດການປົກປ້ອງ Patent - PCT National Phase. ວັນທີສຳຄັນ: ວັນເຜີຍແຜ່ 2023-07-14; ວັນຈົດທະບຽນ/ອະນຸຍາດ 2023-07-10; ວັນໝົດອາຍຸ 2035-12-17. ປະເພດ/ຫ້ອງ: G06F 13/16、H01L 25/065. ນັກປະດິດ/ນັກອອກແບບ: CHATHA, Karamvir, Singh, DU, Yang, LIM, Sung, Kyu, SAMADI, Kambiz. ສະຫຼຸບ: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC…. ຂໍ້ຄວາມນີ້ເນັ້ນຕົວເລກ, ວັນທີ, ປະເພດ ແລະ ຜູ້ຍື່ນ ເພື່ອຫຼຸດຄວາມຄ້າຍຄືນລະຫວ່າງໜ້າ IP; ກວດຂໍ້ມູນທາງການກ່ອນຕັດສິນໃຈ.
P/515
ຮູບໝາຍ
ຂໍ້ມູນພື້ນຖານ
- ປະເພດ
- ສິດທິບັດ
- ເລກຄຳຮ້ອງ
P/515- ສະຖານະ
- ຈົດທະບຽນແລ້ວ
- ຜູ້ຮ້ອງຂໍ
- QUALCOMM INCORPORATED
- ຕົວແທນ
- CONCETTI-LAO CO., LTD
- ວັນຍື່ນ
- 2015-12-17
- ເລກທະບຽນ
P/515- ວັນເຜີຍແຜ່
- 2023-07-14
- ວັນຈົດທະບຽນ / ອະນຸຍາດ
- 2023-07-10
- ວັນໝົດອາຍຸ
- 2035-12-17
- ປະເພດການປົກປ້ອງ
- Patent - PCT National Phase
- ເລກທີຜ່ານຈົດໝາຍ
- 215 · 2023-07-14
- ບຸລິມະສິດ
- US · 14/602,505 · 2015-01-22；US · PCT/2015/066334 · 2015-12-17
- ທີ່ຢູ່ຜູ້ຍື່ນ
- QUALCOMM INCORPORATED · Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 · US
- ທີ່ຢູ່ຕົວແທນ
- CONCETTI-LAO CO., LTD · Lao-Thai Friendship Road, Sokpaluang Village,Sisattanak District, Vientiane Lao PDR, Tel: 312 383 · LA
- ປະເພດສາກົນ
- G06F 13/16 · H01L 25/065
- ສິນຄ້າ / ບໍລິການ
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ຂັ້ນຕອນ
ໝາຍຕາມສະຖານະປັດຈຸບັນ-
ຍື່ນຄຳຮ້ອງ
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ກວດຮູບແບບ
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ກວດເນື້ອໃນ
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ເຜີຍແຜ່
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ອະນຸຍາດ
ການວິເຄາະກ່ຽວຂ້ອງ
ເຊື່ອມກັບຖານຂໍ້ມູນວິສາຫະກິດ LaoBiz.comສິດທິບັດທີ່ຄ້າຍກັນ
ສະຫລຸບ
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.
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