专利 已注册

DESIGN OF HRD DESCRIPTOR AND BUFFER MODEL OF DATA STREAMS FOR CARRIAGE OF HEVC EXTENSIONS

Overview

本页收录老挝专利「DESIGN OF HRD DESCRIPTOR AND BUFFER MODEL OF DATA STREAMS FOR CARRIAGE OF HEVC EXTENSIONS」的公开登记要点,由 QUALCOMM INCORPORATED 于 2015-10-15 提交申请,当前状态为已注册。关键编号与类型标注为 申请号 P/499 / DIP 编号 LAP499 / 主管局代码 LA / 保护类型 Patent - PCT National Phase。时间线要点:公开/公告日 2023-07-14;授权日 2023-07-10;届满/失效参考日 2035-10-15。发明人 / 设计人包括 HENDRY, Fnu、RAMASUBRAMONIAN, Adarsh Krishnan、WANG, Ye-Kui。代理机构 / 代理人记载为 CONCETTI-LAO CO., LTD。公开摘要提示:A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timi…。LaoBiz 将商标、专利与外观设计公开字段整理为可读摘要,并尽量降低页间样板重复;不做权属或侵权结论。

专利 老挝 DIP

申请号 P/499
申请日期 2015-10-15
注册/授权日 2023-07-10
申请人 QUALCOMM INCORPORATED
代理机构 CONCETTI-LAO CO., LTD
类别

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基础信息

类型
专利
申请号
P/499
状态
已注册
申请人
QUALCOMM INCORPORATED
代理机构
CONCETTI-LAO CO., LTD
申请日期
2015-10-15
注册号
P/499
公开/公告日
2023-07-14
注册/授权日
2023-07-10
届满日
2035-10-15
国际分类
商品 / 服务

办理流程

根据当前状态动态标注
  1. 提交申请
  2. 形式审查
  3. 实质审查
  4. 公开
  5. 授权

关联分析

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摘要

A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timing and Hypothetical Reference Decoder (HRD) descriptor. The HEVC timing and HRD descriptor comprises a target schedule index syntax element indicating an index of a delivery schedule. The video processing device may identify, based on a set of parameters, a syntax element in an array of syntax elements in a video parameter set (VPS). The set of parameters may comprise a parameter having a value equal to a value of the target schedule index syntax element. The video processing device may identify, based on an index specified by the identified syntax element, a particular HRD parameters syntax structure in a plurality of HRD parameters syntax structures as being applicable to a particular elementary strea

A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timing and Hypothetical Reference Decoder (HRD) descriptor. The HEVC timing and HRD descriptor comprises a target schedule index syntax element indicating an index of a delivery schedule. The video processing device may identify, based on a set of parameters, a syntax element in an array of syntax elements in a video parameter set (VPS). The set of parameters may comprise a parameter having a value equal to a value of the target schedule index syntax element. The video processing device may identify, based on an index specified by the identified syntax element, a particular HRD parameters syntax structure in a plurality of HRD parameters syntax structures as being applicable to a particular elementary strea

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