DESIGN OF HRD DESCRIPTOR AND BUFFER MODEL OF DATA STREAMS FOR CARRIAGE OF HEVC EXTENSIONS
The following summary describes a Laos Patent titled “DESIGN OF HRD DESCRIPTOR AND BUFFER MODEL OF DATA STREAMS FOR CARRIAGE OF HEVC EXTENSIONS”, filed by QUALCOMM INCORPORATED on 2015-10-15; current status: Registered. Identifiers include application No. P/499; DIP id LAP499; protection kind Patent - PCT National Phase. Key dates: publication 2023-07-14; grant 2023-07-10; expiry reference 2035-10-15. Inventor(s)/designer(s): HENDRY, Fnu, RAMASUBRAMONIAN, Adarsh Krishnan, WANG, Ye-Kui. Abstract hint: A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timi…. This prose is informational only and does not constitute legal advice, ownership proof or an infringement opinion.
P/499
Mark
Key facts
- Type
- Patent
- App. no.
P/499- Status
- Registered
- Applicant
- QUALCOMM INCORPORATED
- Agent
- CONCETTI-LAO CO., LTD
- Filing date
- 2015-10-15
- Reg. no.
P/499- Publication
- 2023-07-14
- Registration / grant
- 2023-07-10
- Expiry
- 2035-10-15
- Protection kind
- Patent - PCT National Phase
- Gazette
- 215 · 2023-07-14
- Priority
- US · 14/883,256 · 2015-10-14；US · 62/064,414 · 2014-10-15；US · PCT/2015/055712 · 2015-10-15
- Applicant address
- QUALCOMM INCORPORATED · Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714 (US) · US
- Agent address
- CONCETTI-LAO CO., LTD · Lao-Thai Friendship Road, Sokpaluang Village,Sisattanak District, Vientiane Lao PDR, Tel: 312 383 · LA
- Nice / IPC classes
- —
- Goods / services
- —
Process
Steps follow the current public status-
Filed
-
Formal examination
-
Substantive examination
-
Published
-
Granted
Related records
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Abstract
A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timing and Hypothetical Reference Decoder (HRD) descriptor. The HEVC timing and HRD descriptor comprises a target schedule index syntax element indicating an index of a delivery schedule. The video processing device may identify, based on a set of parameters, a syntax element in an array of syntax elements in a video parameter set (VPS). The set of parameters may comprise a parameter having a value equal to a value of the target schedule index syntax element. The video processing device may identify, based on an index specified by the identified syntax element, a particular HRD parameters syntax structure in a plurality of HRD parameters syntax structures as being applicable to a particular elementary strea
A video processing device obtains a data stream comprising a plurality of elementary streams and a High Efficiency Video Coding (HEVC) timing and Hypothetical Reference Decoder (HRD) descriptor. The HEVC timing and HRD descriptor comprises a target schedule index syntax element indicating an index of a delivery schedule. The video processing device may identify, based on a set of parameters, a syntax element in an array of syntax elements in a video parameter set (VPS). The set of parameters may comprise a parameter having a value equal to a value of the target schedule index syntax element. The video processing device may identify, based on an index specified by the identified syntax element, a particular HRD parameters syntax structure in a plurality of HRD parameters syntax structures as being applicable to a particular elementary strea
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